Hi All,

We are looking for FPGA Logic Designer for remote Opportunity

Exp: 10+ Years

Work mode: Remote

Time zone: PST (Flexible)

Role Overview

We are seeking a veteran FPGA Logic Designer to drive the development and integration of high-speed serial interfaces. This role requires an expert-level understanding of SerDes architecture and high-speed protocols. You will be responsible for the full design lifecycle, with a specific focus on $Xilinx$ or $Altera$ $GT$ transceivers and complex protocol stacks.

Core Technical Requirements

• High-Speed SerDes Expertise: 10+ years of hands-on experience with Xilinx (GTY/GTM) or Altera/Intel (E-Tile/P-Tile/F-Tile) transceiver integration.
• Protocol Mastery: Deep technical knowledge of at least two of the following: UCIe, PCIe (Gen5/6), CXL, or Ethernet (400G/800G).
• Sub-layer Architecture: Strong background in MAC/PCS-PMA design and troubleshooting.
• Logic Design: Expert proficiency in Verilog/SystemVerilog for high-performance RTL design and timing closure in the Bay Areas most demanding hardware environments.

Key Responsibilities

• Design and implement FPGA logic for cutting-edge high-speed communication interfaces.
• Optimize $MAC/PCS$ layers for low latency and high throughput.
• Perform complex timing closure and hardware validation for $UCIe/CXL$ ecosystems.